-----------------------------------------------------------------------------
-- The router_sl1 pack :                                                   --
--  Designed by Dobkin Rostislav(Reuven).                                  --
--  Date : 07.2004                                                         --
--  Last edit : 25.12.2004                                                 --
-----------------------------------------------------------------------------
-- The package of synchronous roter with 1 SL.                             --
-----------------------------------------------------------------------------
-- Revisions:
--  13.06.07: Changing vcac_idx_out_type -- will pass decimal values instead of one-hot. 
 
library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;


-----------------------------------------------------------------------------
package router_pack is 
-----------------------------------------------------------------------------

 -- Constants declaration section : --
 constant num_of_ports_con           : integer := 5 - 1 ;     -- Number of ports excluding one. 
 constant num_of_ports_log_con       : integer := 2 ;         -- Number of ports excluding one. 

 constant flit_width_con             : integer := 10; --+8+16+32+64;        -- Flit width (8 bits + 2 bits of type).
  
 constant msl_ind_width              : integer := 2;          -- Two bits are used for SL indication.

 constant flit_type_width_con        : integer := 3;           -- can take 3 values.

 constant flit_sl_format_h           : integer := msl_ind_width+flit_width_con-1; -- "00"-SL=0, "01"-SL=1, "10"-SL=3, "11"-SL-4 (highest).
 constant flit_sl_format_l           : integer := flit_sl_format_h-1;

 constant flit_type_format_h         : integer := flit_width_con-1; -- "01"-Header, "00"-Body, "10"-Tail.
 constant flit_type_format_l         : integer := flit_type_format_h-1;

 -- Changed to: 01, 00, 10
 --constant head_type_con              : integer := 0; -- "00";
 --constant body_type_con              : integer := 1; -- "01";
 --constant tail_type_con              : integer := 2; -- "10";

 constant addr_format_h              : integer := flit_type_format_l-1; 
 constant addr_format_l              : integer := addr_format_h-1; 
 
 constant num_of_sl_con              : integer := 4;    -- number of service-levels.

 constant ctrl_latch_delay_line_length_con     : integer := 2;    -- number of inverters in delay line;
 constant delay_line_length_con                : integer := 3;    -- header delay linenumber of inverters in delay line;
 constant data_latch_spa_delay_line_length_con : integer := 2;    -- number of inverters in delay line;

 constant INIT   : std_logic := '0';
 constant NORMAL : std_logic := '1';

 constant mutex4_width_c : integer := 4;
 constant mutex8_width_c : integer := 8;
 
 constant num_of_vc_con   : integer := 2;
 constant vc_width        : integer := 1; -- number of bits for VC indication.
 constant flit_v_format_h : integer := flit_sl_format_h+vc_width;
 
 constant flit_size_c : integer := vc_width+msl_ind_width+flit_width_con;

 -- Types declaration section : --
 type ssl_multiple_ports_data_bus_type    is array (0 to num_of_ports_con-1) of std_logic_vector(flit_width_con-1 downto 0);
 type ssl_router_mult_ports_data_bus_type is array (0 to num_of_ports_con)   of std_logic_vector(flit_width_con-1 downto 0);

 type msl_multiple_ports_data_bus_type    is array (0 to num_of_ports_con-1) of std_logic_vector(flit_width_con-1 downto 0);
 type msl_router_mult_ports_data_bus_type is array (0 to num_of_ports_con)   of std_logic_vector(vc_width+msl_ind_width+flit_width_con-1 downto 0);


 type router_mult_ports_cred_bus_type is array (0 to num_of_ports_con)   of std_logic_vector(num_of_sl_con-1 downto 0);


 type rr_table_type is array (0 to (2 ** (num_of_ports_con+2) -1)) of integer range 0 to num_of_ports_con-1;
 constant rr_table_con : rr_table_type := (0, 0, 1, 1,
                                           2, 2, 2, 2,
                                           3, 3, 3, 3,
                                           3, 3, 3, 3,
                                           
                                           0, 0, 1, 0,
                                           2, 0, 2, 0,
                                           3, 0, 3, 0,
                                           3, 0, 3, 0,
                                           
                                           0, 0, 1, 1,
                                           2, 0, 1, 1,
                                           3, 0, 1, 1,
                                           3, 0, 1, 1,
                                           
                                           0, 0, 1, 1,
                                           2, 2, 2, 2,
                                           3, 0, 1, 1,
                                           2, 2, 2, 2);

 -- MSL-IP output port interfaces: --
 type signaling_ssl_bus_type is array (0 to num_of_vc_con-1) of std_logic_vector(num_of_ports_con-1 downto 0); -- each VC goes to num_of_ports_con-1 ports.
 type signaling_msl_bus_type is array (0 to num_of_sl_con-1) of signaling_ssl_bus_type; -- for each SL there is a group of VCs that goes to num_of_ports_con-1 outptu ports. 

 type data_ssl_bus_type      is array (0 to num_of_vc_con-1) of std_logic_vector(flit_width_con-1 downto 0);  -- data bus from each VC of flit width (no VC info is saved)
 type data_msl_bus_type      is array (0 to num_of_sl_con-1) of data_ssl_bus_type;

 -- For MSL-OP inpur port interface:  
 type data_msl_op_bus_type   is array (0 to num_of_ports_con-1) of data_msl_bus_type;
 
 -- SVC-SSL-OP data interfaces: to all ports x all VCs x data
 type data_ssl_op_bus_type   is array (0 to num_of_ports_con-1) of data_ssl_bus_type;
 type data_to_ssl_op_in_msl_type is array (0 to num_of_sl_con-1) of data_ssl_op_bus_type;
 
 type msl_arb_cur_port_type  is array (0 to num_of_ports_con-1) of integer range 0 to num_of_ports_con-1;

 -- VCAC signals: --
 --type vcac_idx_out_type is array (0 to num_of_vc_con-1) 
 --    of signaling_ssl_bus_type;
 -- 13.06.07:
 subtype vc_op_idx_type is integer range 0 to (num_of_vc_con*num_of_ports_con);

 type vcac_idx_out_type is array (0 to num_of_vc_con-1) 
     of vc_op_idx_type; -- one addition value is "invalid"

 
 type ipidx_arr_type is array (0 to num_of_sl_con-1) of vcac_idx_out_type;

 type data_mvc_bus_type is array (0 to num_of_vc_con-1) of std_logic_vector(flit_width_con-1 downto 0);
 
-----------------------------------------------------------------------------
end router_pack;
-----------------------------------------------------------------------------

 
package body router_pack is

end router_pack;
